Architecture All Access: Meteor Lake - Advanced Packaging | Intel Technology
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- Опубликовано: 26 июн 2024
- "Intel® Core™ Ultra mobile processors, codename Meteor Lake represent Intel's biggest shift in client SoC architecture in 40 years!
In Architecture All Access Season 3, Episode 5, Pat Stover, Vice President in Technology Development at Intel, walks us through an all-access look into the innovative advanced packaging technologies Intel developed for Meteor Lake. Packaging once just connected power and signaling but advanced packaging opens new opportunities for chip design, transitioning us from a system-on-chip to system-on-package. In Meteor Lake, high bandwidth interfaces are pivotal. That makes Foveros 3D Packaging Technology the perfect match. With its low power, low latency, and high interconect density, it unlocks new levels of scalability, allowing us to select the best transistors for specific tasks across different tiles. Pat unpacks the details of Foveros as well as the process for assembling Meteor Lake.
Architecture All Access is a master class technology series, featuring Senior Intel Technical Leaders taking an educational approach in explaining the historical impact and future innovations in their technical domains.
Watch Season 3 intro video here: • Architecture All Acces...
Watch Season 3 Episode 1: Meteor Lake Architecture Overview here: • Architecture All Acces...
Watch Season 3 Episode 2: Meteor Lake 3D Performance Hybrid Architecture & Intel Thread Director here: • Architecture All Acces...
Watch Season 3 Episode 3: Meteor Lake GPU Architecture here: • Architecture All Acces...
Watch Season 3 Episode 4: Meteor Lake Artificial Intelligence here: • Architecture All Acces...
00:00 Introduction
00:14 Meet Pat Stover, Intel VP of Technology Development
01:01 The need for advanced packaging
01:35 Transitioning to System on a Package
01:59 OPIO with Haswell in 2013
02:13 EMIB with Stratix 10 in 2017
02:37 Foveros with Lakefield in 2020
02:48 Co-EMIB with Ponte Vecchio in 2022
03:13 Foveros 3D Packaging in Meteor Lake
04:27 Foveros base tile characteristics
05:09 Assembling Meteor Lake
06:33 Wrapping up
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I am shocked because intel achieved MacBook Pro 2023 level of BATTERY LIFE in Chiplet/Tiles architecture and still video editing on ULTRA 7 155H is FASTER than M2 Pro/M3 pro in Davinchi resolve 18 using H.264 or H.265.
Hp pavilion Plus 14 (68 Wh) with #AMD 7840U has 10 to 11 hours of BATTERY.
Hp spectre x360 14 (68 Wh) with #Intel Core ULTRA 7 155H has 14 to 15 hours of BATTERY. 😱
Intel laptops BATTERY life is as good as MacBook Pro 2023 even though Intel is using Tiles/Chiplet.
Impressive🤯
💪
I was under the impression battery life was OK
@@AndrewMellor-darkphoton what?
@@HDRPC not the impression I got from reviews
When will we get 2nm with backside power deliver
how many effective gates in gaafet transistor with backside power delivery
What can you say about durability, long lifespan of Power management IC units in Chiplet
But in meteor lake foveros looks like emib, I was thinking that foveros it's about chip on chip direct connection and emib it's about horizontal connection but looks like foveros can used for horizontal connections too, what's the difference in this case in meteor lake 🤔
I need desktop cpu have dual cpu support and xeon have quad cpu support. so you can sell more cpu
So why does Meteor Lake only have 6 P Cores, given that it is using a denser node than Intel 7, which had 8 P cores? You have more transistor densityin Meteor Lake, but yet less P cores. Why?
What about the neural engine and more powerful gpu
Also not all of it is made of Intel latest node
@@Intel101-pe1et I know meteor lake uses a multitude of different nodes, some external, some internal, and stitches them together using foveros.
But the cpu core complex is built on Intel 4. Redwood cove and crestmont. On Intel 7, golden cove and raptor cove have up to 8 p cores. On Intel 4, redwood cove is limited to 6 p cores. Why the regression in the maximum number of p cores?
As an example, when Apple moved from TSMC 5 and 4 nm to 3nm, Apple used the increased transistor density to include more P cores (compare m3 max to M2 Max). Yet Intel has done the opposite.
Why ?
@@j340_official Well, it depends on which CPU line you are referring to. RPL-P which is what most directly compares gen-to-gen with MTL, had 6+8 cores with the highest core-count SKU. MTL retains similar core counts with 6+8+2 cores. The benefit of the new node is used to enable the use of RWC and CMT cores (new microarchitectures which should enable higher IPC) and significantly higher efficiency.
So if you compare the proper CPUs, Intel has not regressed in core count, they have remained the same. The CPUs you might be referring to (HX or S) are on RPL-R with 8+16 cores. The H/P series SKUs are not for the sort of devices that would benefit far more from efficiency gains than from core count gains. The lower complexity, cost, and power consumption of keeping the core count the same makes far more sense in this line.
@@AlexSchendelthank you. When you put it that way I see what you mean.
I was looking at it from max p core count of alder/raptor vs meteor lake. But I understand what you’re saying in that the particular meteor lake product on the market is a P-series sku. So comparing that to the predecessor.
But you have to understand why intel’s new product naming scheme is a little confusing. Intel refers to meteor lake as “core ultra”, and raptor lake refresh hx as “core.” For most English speaking people, something that is “Ultra” has better features than something that is not ultra. Yet with meteor lake, the max p core count of the Ultra sku is 6, whereas the max p core count of the non-ultra sku (i.e., RPL-refresh) is 8. Also the non-ultra RPL refresh hx sku will apparently have Barlow ridge TB5 support and the Ultra sku will not. So the non-ultra sku in part has better features than the ultra sku. Confusing!
Now I understand that meteor lake core ultra is really meteor lake-P. A low power sku. Much better integrated graphics than before. And also an NPU.
Thank you for clarifying!
when I can have xeon 1000b transistors
2030-ish. Pat aims to have 1 trillion transistors on a single package by 2030. That of course will probably be more like an accelerator or the combo accelerator+CPU on a single package that the industry is tending to move towards
If your fabs are so good why even use TSMC for specific tiles instead of going full home made?
1. Intel functioned as an IDM with monolithic products until very recently which means that "mature" (older and cheaper) nodes do not make sense to keep around.
2. Intel is still ramping high-volume manufacturing on cutting edge processes, so it might not make sense to throw everything on internal processes yet.
3. Intel is also in the midst of a massive fab build out across the world to provide more capacity for the foundry business.
4. Intel's existing processes tend to be specialized for CPUs. Lower density and higher performance on the logic variant, and higher density otherwise. TSMC offers many more options for customization of nodes because they have such a wide repertoire. As Intel has gotten involved in more than just CPUs, TSMC might currently have better node options.
5. Since many of the IPs that Intel is using came from other companies which Intel has purchased (Habana Gaudi, Mobileye, Altera, Movidius' NPU, etc.) and those companies were originally fabless companies which relied on TSMC for fabbing their IP. Takes time to pivot away to the internal foundry, especially because Intel has been working as an IDM for decades and thus doesn't have the same transparency and PDK offerings as TSMC might. Intel has been quickly bridging that gap over the past couple years with their pivot to IFS.
I guess we'll see what happens in the future, but with Intel's transition to independently reporting P/L for the foundry, it might make the internal foundry simply another option compared to TSMC rather than the default.